The present invention generally relates to circuit having level converting circuits, and more particularly to a circuit having a level converting circuit suited for converting a logic level used in gallium arsenide (GaAs) devices (hereinafter simply referred to as GaAs logic level) into a logic level of an emitter-coupled logic (ECL) devices (hereinafter simply referred to as ECL level).
In order to realize high-speed operation in systems, there recently are systems which use GaAs devices. However, with the present compound semiconductor technology, it is difficult to form the system solely from GaAs devices. For this reason, there is a demand to use the GaAs devices together with existing ECL circuits or the like which operate at high speeds. In this case, it becomes necessary to use a level converting circuit for converting the GaAs logic level into the ECL level.
Conventionally, when converting the GaAs logic level into the ECL level, a level converting circuit 2 is provided within a GaAs device 1 as shown in FIG. 1. The level converting circuit 2 converts an output level (GaAs logic level) of an internal gate circuit 3 of the GaAs device 1 into the ECL level and supplies the ECL level to an ECL device 4. In other words, the level converting circuit 2 includes two GaAs transistors 5 and 6 which are connected in series between voltage lines V.sub.DD and V.sub.T, where the voltage line supplies a power source voltage V.sub.DD (+2 V) and the voltage line V.sub.T supplies a voltage VT derived from the ECL device 4. A terminal resistor RT is connected in parallel with the GaAs transistor 6, and the ECL level is supplied to the ECL device 4 via the terminal resistor RT.
On the other hand, the ECL device 4 uses three voltages which are a ground voltage (0V), the voltage V.sub.T (-2V) and a power source voltage V.sub.EE (-5.2V). The ECL level from the level converting circuit 2 is applied to a base terminal of a transistor 8 which is one of emitter-coupled transistors 8 and 9 of an ECL circuit 7 within the ECL device 4. A bias voltage Vref which is generated based on the voltages GND and V.sub.EE is applied to a base terminal of the transistor 9.
But according to the level converting circuit 2 provided within the GaAs device 1, it is necessary to set the resistance of the terminal resistor RT to 50 ohms and obtain an amplitude of 0.8V in order to ensure normal operation of the ECL circuit 7. Thus, there are problems in that the power consumption of the GaAs transistors 5 and 6 becomes large and patterns of these GaAs transistors 5 and 6 become large making it difficult to form the circuit in the form of an integrated circuit having a large integration density.
In addition, since the GaAs logic level output from the GaAs internal gate circuit 3 is dependent on the power source voltage V.sub.DD, the ECL level which is output from the level converting circuit 2 is also dependent on the power source voltage V.sub.DD. This means that the ECL level applied to the transistor 8 of the ECL circuit 7 is dependent on the power source voltage V.sub.DD. However, the bias voltage Vref which is applied to the other transistor 9 of the ECL circuit 7 is independent of the power source voltage V.sub.DD. As a result, there is a problem in that the operating margin of the ECL circuit 7 becomes small and insufficient when the power source voltage V.sub.DD undergoes a deviation due to some reason, for example.
The GaAs device 1 is virtually unaffected by a temperature change, but the voltage level within the ECL circuit 7 changes responsive to the temperature change. For this reason, although the ECL level which is applied to the transistor 8 from the GaAs device 1 is virtually unaffected by the temperature change, the reference voltage Vref which is generated within the ECL device 4 undergoes a change responsive to the temperature change and the operating margin of the ECL circuit 7 becomes small with respect to the temperature change. FIG. 2 shows output voltage V.sub.OUT versus temperature Ta characteristics of an ECL circuit and a GaAs circuit. In FIG. 2, the dotted line indicates the output voltage V.sub.OUT of the ECL circuit which changes at a rate of approximately 1.0 mV/.degree. C., and the solid line indicates the output voltage V.sub.OUT of the GaAs circuit which is approximately constant regardless of the temperature.